1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a fabrication method for the device. In particular, the invention relates to a nonvolatile semiconductor memory and a fabrication method that achieves a highly integrated circuit where two memory cell columns share a single bit line.
2. Description of the Related Art
As an example of conventional technology, a NAND EEPROM has a single bit line for each NAND column. When bit line BLk is a write-in bit line, and bit lines BLk+1 and BLk−1 are write-in control bit lines, respectively, during write-in, a predetermined gate voltage Vsg is applied to a bit line BL side select gate transistor SG1, and a sufficiently low voltage VBLpgm is applied to a bit line BL that is utilized to write-in. The aforementioned gate voltage Vsg is set to a voltage that allows the select gate transistor SG1 to turn on as opposed to the low voltage VBLpgm. A sufficiently high voltage VBLinhibit is applied to the bit lines BLk+1 and BLk−1 that are utilized to control write-in. The voltage VBLinhibit is set to a voltage level that sufficiently allows the aforementioned select gate transistor SG1 to turn off. A NAND memory cell transistor utilized by a corresponding bit line BL for write-in that has received a sufficiently low voltage VBLpgm is written when the select gate transistor SG1 is turned on so as to apply VBLpgm to the memory cell transistor. Thus, the channel voltage for the memory cell transistor is sufficiently reduced. Also, a NAND memory cell transistor utilized by corresponding bit lines BLk+1 and BLk−1 to control write-in that has received a sufficiently high voltage VBLinhibit is not written when the select gate transistor SG1 is turned off because the memory cell transistor channel voltage rises through capacitive coupling with a control gate CG. This state is a write-in controlled state, as disclosed by K. Imamiya, et.al., “A 125 mm2 1 Gb NAND Flash Memory With 10 M Bytes/s Program Speed”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002, pp. 1493-1501.
However there is a problem in the conventional technology. When the device region pitch of NAND memory cell transistors is 2F, the size of the contact connecting the bit line BL to the diffusion layer of the bit line BL side select gate transistor must be larger than F considering misalignment and largely depending on exposure techniques. Here, F denotes the minimum processing dimension. Therefore, the interval between adjacent bit line contacts CB connecting neighboring bit lines BL to the respective diffusion layers of the bit line BL side select gate transistors is less than F. Accordingly, there is a large probability of an electrical short circuit will occur. Naturally, since each bit line BL has to be connected to corresponding bit line contact CB, which is used to connect the diffusion layer of a bit line BL side select gate transistor, processing of the bit lines and contacts is extremely difficult.
The present invention provides a nonvolatile semiconductor memory and a fabrication method for the device, which allow high integration of a NAND EEPROM, and allows bit line contacts CB, each connecting a bit line BL to the diffusion layer of a bit line BL side select gate transistor, to be arranged with a pitch that is twice the NAND column pitch, where two NAND columns share a single bit line BL, particularly in NAND EEPROM.